1. Field of the Invention
The present invention relates to a semiconductor device, semiconductor element, and a substrate.
2. Description of the Related Art
FIG. 12 shows an example of a configuration of a semiconductor device 100A according to the related art fabricated as a display driver using the COF (Chip On Film) method.
As shown in FIG. 12, the semiconductor device 100A includes a semiconductor element 12 configured as an IC (Integrated Circuit) chip, and an insulating film 18 constituted by a film as a substrate, and the semiconductor element 12 is mounted on the insulating film 18.
The semiconductor element 12 includes a resistance ladder 80 which is formed by series-connected four resistors 80a, 80b, 80c, and 80d disposed in respective predetermined positions and which generates a reference voltage to serve as a reference for an output voltage to be output from the semiconductor element 12 to a display. The semiconductor element 12 also includes five resistant ladder electrodes 82a, 82b, 82c, 82d, and 82e formed along a first edge of the semiconductor element 12. The semiconductor element 12 also includes semiconductor element internal wirings 86 for connecting the resistance ladder electrode 82a and the resistance ladder electrode 82e with the ends of the series connection of the resistance ladder 80, and includes a semiconductor element internal wiring 88 for connecting the resistance ladder electrodes 82b to 82d with intermediate connecting parts of the series connection of the resistance ladder 80. An Au (gold) bump 84a, an Au bump 84b, an Au bump 84c, an Au bump 84d, and an Au bump 84e are provided on a surface of the resistance ladder electrode 82a, a surface of the resistance ladder electrode 82b, a surface of the resistance ladder electrode 82c, a surface of the resistance ladder 82d, and a surface of the resistance ladder electrode 82e, respectively.
The insulating film 18 includes input side outer leads 22 and output side outer leads 24 which are provided in a non-mounting region of the insulating film 18 where the semiconductor element 12 is not mounted and which serve as terminals for external connection. The insulating film 18 includes resistance ladder connection nodes 21a which are formed in a mounting region of the insulating film 18 where the semiconductor element 12 is formed and which are connected to the resistance ladder electrodes 82a, 82b, 82c, 82d, and 82d, respectively. The film 18 also includes resistance ladder connection patterns 21 which are formed to extend from a non-mounting region into the mounting region for connecting the input side outer leads 22 and the resistance ladder connection nodes 21a. 
Signals are input to the semiconductor device 100A through the input side outer leads 22 and subjected to predetermined conversion in the semiconductor element 12, and the converted signals are output through the output side outer leads 24. For easier understanding, FIG. 12 shows only the resistance ladder 80 among internal circuits in the semiconductor element 12, and other internal circuits (e.g., a logic unit, a level conversion unit, a latch unit, a D-A conversion unit, and a grayscale voltage generating unit) are omitted in the illustration.
As shown in FIG. 12, in general, the resistance ladder is disposed in a fold configuration because of the dimension of the shorter sides of the semiconductor element 12 and the area to accommodate the same. The resistance ladder shown in FIG. 12 has a circuit configuration as shown in FIG. 13 by way of example. In order to prevent fluctuations of the characteristics of this circuit, the semiconductor element internal wirings 86 and 88 must have low impedance. In particular, the impedance of the semiconductor element internal wirings 86 must be kept as small as possible. For this reason, the line width of the semiconductor element internal wirings 86 and 88 must be great, and a problem has therefore arisen in that the surface area of the semiconductor element 12 must be made great accordingly.
As a technique which can be used as a solution to this problem, Japanese Patent Application Laid-Open No. 2006-80167 has disclosed a technique for reducing the size and weight of a semiconductor device. Specifically, in a semiconductor device wherein a semiconductor element is mounted on a substrate by connecting a wiring pattern formed on the substrate and a first connection terminal formed in a first connection terminal forming region in a peripheral part of the semiconductor element, a second connection terminal form inputting or outputting a signal to or from the semiconductor element is also provided outside the first connection terminal forming region of the semiconductor element. In addition, the substrate is provided with a connection wiring for connecting the second connection terminal with the wiring pattern and/or connecting the second connection terminal with another second connection terminal.
According to this technique, since connection between a circuit in a semiconductor element and a wiring pattern can be provided by a wiring for connection, a wiring which has been routed on or under a surface of the element can be replaced with the connection wiring, which allows the size and weight of the semiconductor element to be reduced.
Although the technique disclosed in the document makes it possible to reduce wirings associated with output from circuits in a semiconductor element, no attention is paid to signals input to a semiconductor element. In particular, the reduction of the size of a semiconductor element is not sufficiently realized when it is attempted based on the existing concept that a first connection terminal is to be formed in a peripheral part of a semiconductor element.